The bit rate for a waveform with a period of 36 ms is 27.7 kbps. Due to the 50% duty
cycle, a transition occurs at the middle of a bit window, and logic levels may change
between bit windows. Therefore, the data signal toggling rate is 55.4 kbps. The sampling
rate ( fs) must be least two times faster than the toggling frequency ( ft) of the target signal:
fs??23ft. Since the data signal toggling rate is 55.4 kbps ( ft) the minimal sampling rate is
110.8 kbps or four times oversampling. However, the A parameter of the description tells
us the typical ?¬‚uctuation that might occur in the signal, which was speci?¬?ed as 12.5%.
Thus, a minimum of eight times oversampling should be used for edge detection and
synchronization.
An overview of the general waveform detection circuit is shown in Figure 3.14. This
circuit contains a preamble detection circuit, an edge detection circuit used for synchronization
with the incoming waveform, a timer circuit for signaling the controlling state
machine to change states, a sampling register ?¬?le for converting levels and edges into
decoded bit values, and a serial-to-parallel converter for building bytes from the incoming
bits. The system clock speed is also variable based on the required sampling by the circuit.
The data transmission begins after a valid preamble is detected by the start signal. The
edge detection circuit shown in Figure 3.
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