15 is used to keep in synchronization with the
incoming waveform. Every system cycle in which the value changes signals the timer that
an edge has occurred.
The timer circuit shown in Figure 3.16 controls the sampling times to check for levels or
value changes in the incoming waveform. The timer circuit contains a counter that counts
system cycles until its next sampling window. Thus, the hardware library contains parameters
for the number of time points n to sample, the number of cycles to count between each
sample N0, N1, . . . , Nn1 and the bit width of the counter which is log2 max(N).
The timer signals become inputs into an automatically generated ?¬?nite state machine
(FSM) controller circuit. The FSM uses the timer signals and the sampling registers block to
determine the actual encoded values. The sampling registers circuit, shown in Figure 3.17,
preamble: pre????™1??™ after 0 us & ??™0??™ after 15 us & ??™1??™ after 10 us
& ??™0??™ after 5 us & ??™1??™ after 10 us & ??™0??™ after 5 us....;
FIGURE 3.12
Preamble textual representation example.
transmission: bitOrder??least; byteOrder??most;
byteSize??9; stopBits??1;
FIGURE 3.13
Serial transmission characteristics.
44 RFID Handbook: Applications, Technology, Security, and Privacy
samples two data values when signaled by the controller and reports back whether there
has been a rising edge (0 followed by a 1), a falling edge (1 followed by a 0), or a constant
level 1 or 0.
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