Based on these values, the controller traverses states to match one of the bit
conditions speci?¬?ed in the textual description. It can also base this on one or more previous
values seen in the serial stream with the previous_value signal.
The controller uses the synchronization signal Edge_out to tell the timer when to reset
with the Sync_reset signal. For cases where the bit window is not ?¬?xed, a bit may be
determined before all timers have expired as with PIE encoded values of 0. The controller
can reset the timer early in these cases to begin looking for the next bit.
Finally, once a bit is determined it is fed into the serial-to-parallel circuit. This circuit,
shown in Figure 3.18, has parameters such as the number of bits per byte and the direction
of shifting. For MSb ?¬?rst the circuit shifts bits into the register from the left and for LSb ?¬?rst
the circuit shifts bits from the right. When buffering the whole packet a similar shifting
technique is used for most and least signi?¬?cant bytes (MSB and LSB).
Edge
detector
Edge_out
Timer
Sampling_clk.
Sync_reset
t0
t1
tn ??’1
Sampling
registers
(first and second
level
sampling points)
Sampling_clk.
Data In
Feature_type
Serial_to_parallel
and
bit counter
Sampling_clk
Bit_value
Byte
Previous_Value
FSM
Sampling_clk
Edge_out
Sync_reset
t0
t1
tn ??’1
Bit_count
Samp_en1
Samp_en2
Shift_en
Bit_count_en
Data_In
Sampling_clk
Samp_en1
Samp_en2
Shift_en
Bit_count_en Bit_count
Previous_Value
Bit_value Feature_type
start
FIGURE 3.
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