14
General waveform detection circuit.
XOR
FIGURE 3.15
Edge detection circuit.
Design Automation for RFID Tags and Systems 45
3.3.3 Physical Layer Synthesis and VHDL Generation
The synthesis process fromthe textual description is primarily based on discovering sampling
points based on the waveform properties. For example, consider the modi?¬?ed Miller encoding
in Figure 3.10. The basic waveforms for 0 and 1 with an inverse pulse indicate sampling both
during the pulse and outside the pulse. The synthesis process ?¬?rst selects sampling points in the
center of a level region, thus at 2 and6.7ms for a 0 and at 2.7, 6.7, and9.05ms for a 1. First, the 9.05
ms is discarded, because the signal is high for all three descriptions. 6.7 ms is retained directly,
because itmatches both the 1 and 0 directly. The 2 and 2.7ms values aredetermined to represent
the same sampling window as they are within stable regions for both the 1 and 0 waveforms.
As a result, any value within the range of 2??“2.7 may be selected for a sampling point.
Match
Counter
tn ??’1 time
t2 time
Array of time points
t1 time
Match
Match t1
t2
tn ??’1
FIGURE 3.16
Timer circuit schematic.
Feature_type
to FSM
Features
look-up table
Sample_v2
Sample_v1
Sampling
register
Sampling
register
Data_In
Data_In
Samp_en2
Samp_en1
FIGURE 3.17
Sampling registers circuit schematic.
Pages:
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114