Each bit waveform is generated with a very simple
controller FSM that uses timers to traverse states and each state outputs one particular
level. This is a fairly straightforward conversion process from the textual representation.
The VHDL code generation is the ?¬?nal phase of the synthesis ?¬‚ow. The structure of the
block is shown in Figure 3.14. Several of the libraries included are parameterized with
VHDL generic constructs for speci?¬?ed parameters including the timer and serial-toparallel
blocks. The FSM controller is entirely generated by the synthesis engine using a
generic for the number of timer signals to include.
3.3.4 Results
Hardware was generated for the ?¬?ve encodings, Manchester, differential Manchester, PIE,
FM0, and modi?¬?ed Miller. The results for the decoders are shown in Table 3.1. Encoders
TABLE 3.1
Decoder Hardware Block Statistics for Five Different Encodings
Encoding Clock (MHz) Area (mm2) Power (mW)
Manchester 0.5 3780 2.9
Differential Manchester 0.5 3520 2.7
Pulse interval (PIE) 6 9264 84.8
FM0 6 6052 44.6
Modi?¬?ed Miller 2 3780 11.9
MSb L-shift or R-shift (including stop bits)
Byte
FIFO or LIFO
(LSB) (MSB)
LSb
FIGURE 3.18
Serial-to-parallel circuit schematic.
Design Automation for RFID Tags and Systems 47
have been omitted because their hardware is trivial compared with the decoders for each
type of encoding.
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