The SuperCISC compiler [32,33] takes advantage of well-known compiler transformations
including loop unrolling, function inlining, and hardware predication to convert
each control dependency into a data dependency creating a combinational representation.
The SDFG for the Query command is shown in Figure 3.25. The need for many potentially
high-power consuming sequential constructs such as registers and clock trees are removed
by this technique. Thus, the resulting SDFG-based hardware implementations are
extremely power ef?¬?cient [34].
The RFID compiler contains both power and area optimization routines. The power
optimizations are described in detail by Jones et al. [34]. The area optimizations attempt to
discover the maximum precision used by signals in the design and propagate that information
through the design to reduce the size of storage elements and synthesized functional
units. The automatically generated design is expected to be less optimal than a hand
design, but provides a reasonable estimate for a system designer to compare different
protocols and different implementation targets.
3.4.4 Results
The RFID design automation ?¬‚ow has been used to implement RFID primitives from a
variety of different standards such as ISO 18000 Part 7, ANSI NCITS 256, ISO 18000 Part 6C,
and ISO 18185 Part 1. The most critical metrics for success with the resulting implementations
are area and power of the resulting tag controller.
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