29b) of the tag programs on the StrongArm, XScale, and EISC processors. Both
ARM-based processors operate in the 250??“400 mW range, whereas the XScale uses signi?¬?-
cantly less energy. The EISC processor uses an order of magnitude less power, but operates
much slower. However, the energy consumed is still less than half of XScale. The energy of
executing Program A on the EISC could not be calculated because of the program size
exceeding the program memory of the EISC board. This is probably re?¬‚ective of a real area
constraint in an RFID tag, as the chip size would be increased because of memory required
for the ?¬?rmware. Thus, a program size optimization might be necessary for actual implementation.
It can be seen that the power consumption of XScale is less than that of StrongArm
though they both implement the ARM Instruction Set Architecture. This is because the
XScale family of microprocessors uses deep pipelines and microarchitectural optimizations
for high performance [42]. Further, the reduced power consumption and greater clock
speed of XScale result in its far lower energy consumption.
3.4.4.2.2 Custom Hardware-Based Tag
Using the RFID compiler, the number of primitives for the custom hardware-based compiler
were scaled up to 40 and implemented in 3 hardware targets, a Xilinx Coolrunner
II CPLD, an Actel Fusion FPGA, and custom cell-based ASIC hardware at 0.
Pages:
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130