16 mm. Initial
results appear in Jones et al. [37]. It should be noted that to ?¬?t all 40 primitives, the largest
Coolrunner II device available (XC2C512) had to be used, but all the primitives comfortably
?¬?t into the smallest Fusion device available (AFS090).
The area and power results for the implementations are presented in Tables 3.2 and 3.3,
respectively. As previously mentioned, the area required by the custom hardware for ASIC
implementation directly impacts the cost. As shown in Table 3.2, the ASIC controller area is
quite low, less than 4300 cells for a 40 primitive controller, which is smaller than the 10s of
kilobytes of memory required in software-based designs. The three implementations
provide levels of power consumption, as shown in Table 3.3. The CPLD power hovers
Microprocessor power comparison
350
300
250
200
150
100
50
0
Program A
Power (mW)
StrongARM power
(a)
Beachmark program Beachmark program
(b)
XScale power EISC power StrongARM energy XScale energy EISC energy
Program B Program C
Microprocessor energy comparison
20
40
60
80
100
120
140
160
180
200
0
Program A
Energy (mJ)
Program B Program C
FIGURE 3.29
Power and energy comparison of tags with different microprocessor cores. (a) Power. (b) Energy.
* Energy calculation is static power consumption multiplied by measured execution time.
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