55%. We note that there is a trend that as primitives are
added the area increase percentage rises. This is in part due to how Design Compiler does
resource sharing. We noticed that this did not occur with other synthesis tools for FPGAs.
TABLE 3.4
Area for Implementing the Gen-2 Primitive Logic on a 0.16 mm ASIC
Prims 1 2 3 4 5
Manual 1.1642 1.1933 1.2288 1.2313 1.3212
Automated 1.1326 1.2159 1.2842 1.2942 1.4606
% Increase with automation 2.71 1.89 4.51 5.11 10.55
Note: ASIC area is 100 mm2.
TABLE 3.5
Resource Utilization for Implementing the Gen-2 Primitive Logic on a Spartan 3 FPGA
Prims 1 2 3 4 5
IOs
Manual 419 419 419 419 419
Automated 419 419 419 419 419
% Increase with automation 0 0 0 0 0
Global Buffers
Manual 2 2 2 2 2
Automated 2 2 2 2 2
% Increase with automation 0 0 0 0 0
Function Generators
Manual 720 757 787 789 817
Automated 713 742 814 814 825
% Increase with automation 0.97 1.98 3.43 3.17 0.98
CLB Slices
Manual 569 572 580 580 588
Automated 559 563 571 571 571
% Increase with automation 1.76 1.57 1.55 1.55 2.89
Dffs or Latches
Manual 1138 1143 1159 1159 1176
Automated 1118 1125 1141 1141 1141
% Increase with automation 1.76 1.57 1.55 1.55 2.98
Design Automation for RFID Tags and Systems 59
Design Compiler does allow resource sharing through use of specialized controls, which
provide an opportunity to reduce this overhead.
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