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Simpli?¬?ed and abstract level hardware block diagram of SDLR.
100 RFID Handbook: Applications, Technology, Security, and Privacy
addition to separate or multiplexed address and data buses. This section presents a
hardware interface and the accompanying software protocol that is involved in communicating
between the host and target unit through the 8 bit HPI.
5.2.5.1 HPI Boot Process
The TMS320C5416 contains 4 k-words of on-chip ROM. A portion of this ROM is used to
store the bootloader code. The MP=MC bit of the processor is sampled at reset and its value
partially determines the con?¬?guration of the DSP. If MP=MC is set low, then the C5416 is
set to microcomputer mode and the bootloader will start execution following reset. The
ROM code bootloader is located at memory address 0xF800.
There are two methods to signal the bootloader that HPI boot is active: INT 2 and
memory location 0x007F. The bootloader checks to see if the INT 2 pin is set to one (active);
if it is, then HPI mode is selected. The bootloader also clears the memory location 0x007F
and uses it as a software ?¬‚ag to show that HPI boot is complete.
A simple way to achieve HPI boot is to connect pin HINT to INT 2 and wait at least 30
clock cycles for the bootloader to become ready. After this time delay the HPI code transfer
process can begin. After completing the code transfer, writing the start-up address to
memory location 0x007F will signal the DSP that the boot is complete.
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