It contains the electrically
erasable programmable read-only memory (EEPROM), which provides instant-on capability
and offers 256 macrocells. EPM3256A device supports in-system programmability (ISP)
and can be easily recon?¬?gured in the ?¬?eld. Each macrocell is individually con?¬?gurable for
either sequential or combinatorial logic operation.
This device is responsible for the interface between the DSP chip and other peripherals
by converting and buffering the signals from the ADC, DAC, PLL, etc., to the McBSP
format, which is acceptable by the DSP chip.
The CPLD has various internal registers, which are mapped to its IO pins. These IO pins
are connected to PLL, LEDs, and several other peripherals that can be controlled by
software.
5.2.7 Analog-to-Digital Converter
The system makes use of an ADS5231 high-speed, dual-channel ADC. The ADS5231 offers
12 bit resolution at sample rates of up to 40 MHz. It is interfaced directly to the CPLD and it
drives its clock signal from the CPLD as well.
5.2.8 UHF Module
The UHF module is responsible for interfacing the DSP to the antenna. A simpli?¬?ed block
diagram of this module is depicted in Figure 5.5. Some blocks of this design may also be
found in Figure 5.3. It operates at 880??“1050 MHz UHF band and is compatible with FCC??™s
part 15.247 rules. These rules specify that a maximum output power of 1W may be
exercised in a frequency-hopping system with at least 50 channels.
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