The maximum dwell
time for each channel is set to 400 ms at any given frequency. The UHF band module is
subject to PLL lock-time and the receiver circuit turn-around time limitations. The locktime
is the time that it takes the PLL to switch from one frequency to another for a given
frequency change to a given frequency tolerance. In order to mitigate the effect of PLL locktime,
a two synthesizer design was chosen. This design allows the system to program the
second PLL to a new frequency while the ?¬?rst one is still operating and then to switch over
to the second PLL when a frequency hop is required. This con?¬?guration prevents the deadtime
during which the reader RF ?¬?eld would be off and no data can be transmitted. In
addition, it reduces the risk of tags??™ brown-out (when the voltage temporarily drops below
the operating voltage level and then recovers).
5.2.8.1 Oscillator
A PSA0965A phase locked loop (PLL) from Z-Communications Inc. is used to generate the
operating frequency. It is a small hybrid circuit block based on a National Semiconductor
LMX2316 PLL IC. This small module generates an output of 3dBm with phase noise
of 1000 dBc=Hz at 10 kHz from the carrier frequency. The output of the oscillator
Contemporary RFID Reader Architecture 103
is bandpass ?¬?ltered and then ampli?¬?ed by 10 dB. The ampli?¬?er output is then subjected to
a ceramic ?¬?lter with center frequency of 915 MHz to remove the strong harmonics and
other unwanted spurious outputs.
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