Our solution is to build a hierarchical lowpower
memory block based on current state-of-the-art nonvolatile memory blocks.
11.2.1 Memory Block Model
Clock gating has been the conventional solution for low-power operation. However, gating
the clock is insuf?¬?cient for our purposes of developing an ultra-low power nonvolatile
memory with capacity many times greater than existing integrated nonvolatile memory
blocks. Thus, our memory design is based on preexisting memory blocks with a 200 byte
capacity optimized for use in passive RFID systems.
Typical RFID systems are implemented in older CMOS technologies such as
0.18??“0.35 mm. Thus, we assume that the power consumed in our system is because of
dynamic power, as static power only becomes a dominant effect at much smaller feature
sizes [1]. And as such the dynamic power or switching power of the system is governed by
the formula shown in the following equation:
P ?? f CVdd
2 (11:1)
where
P is the dynamic power
f is the frequency of operation
C is the capacitance of the circuit
Vdd is the supply voltage
11.2.2 Memory System Architecture
In our ?¬?rst design, we added a power-enable PMOS device in series with the memory
block, as shown in Figure 11.1. This allows only the block that is actually addressed to be
powered, while the remaining blocks remain disconnected from power.
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