To manage which
bank is activated, an address decoder is required to enable which power-enable signal is
asserted. An overview of this architecture is shown in Figure 11.2, where N is the number
of memory blocks and M is the number of inputs to the decoder.
The primary bene?¬?t of the power-gated implementation is that the static and dynamic
powers can both be eliminated from all but the active memory block. The addition of a
series power-enable PMOS device does not affect the average power consumed by the
device, but reduces the peak power consumed by the device. This technique has been
previously applied to I=O buffers to reduce the SSN (simultaneous switching noise)
produced on the supply lines when the output buffers switch [2]. The design implication
on RFID tags relates to the reduction of peak power consumed by the device, in particular
Memory
block
Power enable
Data
FIGURE 11.1
Memory block with power gate.
Minimum Energy=Power Considerations 201
that the peak power requirement in passively powered tags is greatly reduced. A greater
peak power requirement can be problematic as the peak power delivered to the tag is
limited by the power delivered by the reader. Since RFID tags typically operate at a
relatively low frequency (e.g., <500 kHz), the addition of the PMOS device does not
have an adverse impact on the speed of the memory.
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