A0
A1
AM ??’1
Power enable 0
Power-on reset
Precharge
Power-on reset
Precharge
Vdd
FIGURE 11.4
Precharge for the decoder lines.
Reset time period
Power supply
Vdd
0 V
Power-on reset
FIGURE 11.5
Simulation for the precharge transistor with power-on reset.
Minimum Energy=Power Considerations 203
Thus, the power-enable transistor from Figure 11.1 has a Vgs 0 during power-up and
does not turn on.
Xinquan et al. provide an example of a low-power power-on reset circuit that consumes
5.1 mW, shown in Figure 11.6 [4]. However, if the additional power requirement is
problematic for this circuit, a possible solution is to use the burst switch to drive the
power-on reset signal. The reader would transmit on its standard frequency to begin
powering the tag, and after the reset period had expired, transmit on a different frequency
for the burst switch. Thus, the burst switch would activate the power-on reset signal after
the requested duration.
11.2.2.2 Banking Memory Blocks
Typically, the data line from each memory block is directly tied together to create a global
data line. This is possible because only the active bank drives the line avoiding the
potential for multiple drivers. On implementing the architecture from Figure 11.2,
the load capacitance for the data lines increases dramatically as each memory block adds
its output load capacitance to the system, thus signi?¬?cantly increasing the power required
to drive the full memory system.
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