To avoid this, we have grouped the memory blocks into
memory banks. The data lines within the banks are tied together, however, between banks
they are separated by a multiplexer, as shown in Figure 11.7. This accounts for a signi?¬?cant
reduction in required power.
11.2.3 Results
For our fundamental memory building block, we used a model of a 200 byte nonvolatile
memory block built in 0.2 mm CMOS operating at 1.5 V with an active power consumption
of 5 mW. Using this memory block, the memory block was used to construct a memory that
can contain more than 68 KB with a nominal increase in power consumed. This architecture
requires approximately 350 memory blocks arranged into banks of 22 blocks each.
These speci?¬?cations are based on conversations with RFID tag manufacturers that include
VDET REF
IBIAS M3
cd
M5
NOR2
POR
M7
M6
M4
M2
R4
M1
vcc
COMP1
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+
COMP2
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+
Reference
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R2
O
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D
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G
S
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R3
FIGURE 11.6
Power-on reset circuit (Reproduced from Xinquan, L., Weixue, Y., Ligang, and Yu, C., ??????A low quiescent
current and reset time adjustable power-on reset circuit,??™??™ Proceedings of International Conference on ASIC (ASIC),
559??“562, 2005. With permission.)
204 RFID Handbook: Applications, Technology, Security, and Privacy
nonvolatile memory for tags meeting passive standards such as ISO 18000 Part 6C and
have applications that require up to 64 KB of memory.
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