We model the memory block as an inverter with an approximated load capacitance, CL,
based on details of the memory block architecture, as shown in Figure 11.8a. Based on
the memory block speci?¬?cations, we calculated CL as 4.44 pF. Any device that
allows switching could be used to model the dynamic power of the device; however,
the inverter was selected because of its simpli?¬?ed modeling. To this device we added
the power-enable PMOS device in series to the system. The circuit diagram is shown in
Figure 11.8b.
For a passively powered RFID system, the peak power requirement is the determining
factor as to whether the device works correctly. The memory system described in Section
Bank
0
Bank
1
Bank
B-1
Data
Mux
Memory
block
0
Memory
block
1
Data
Cout+ Cwire Memory
block
N/B-1
Address
LSBs
Address
MSBs
Data
Power enable 0 Power enable 1 Power enable N/B-1
FIGURE 11.7
Banked memory architecture.
Vdd
IN OUT
CL
(a)
Vdd
IN OUT
CL
Power enable
(b)
FIGURE 11.8
Dynamic power memory block models. (a) Memory block model. (b) Memory block model with power gate.
Minimum Energy=Power Considerations 205
11.2.2 was implemented in 0.2 mm CMOS technology from TSMC with a combination of
tools from Cadence and Micromagic. Power analyses were conducted with HSpice.
The memory block model from Figure 11.8 was examined both with and without the
PMOS power-enable transistor.
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