The results shown in Table 11.1 suggest that the powerenable
transistor cuts the peak power approximately in half when the device is active as a
result of being in series with the pull-up network. This power reduction is due to the peak
current attenuation from the power-enable transistor current plot shown in Figure 11.9
from a HSPICE simulation.
When combining all of the memory banks, as shown in Figure 11.2, the power-up time
and in particular the delay have a signi?¬?cant impact on the power consumed by the
memory. For example, with a power-up time tP??100 ms and an ideal ramp up of
the power-enable inputs tD??0, average power consumption is approximately 25.5 nW.
However, as the power-enable delay increases linearly, the power consumption increases
exponentially to reach 25.4 mW for tD??40 ms based on the simulations as indicated in
Figure 11.3. tD was varied between 26 and 40 ms to study the peak currents in more detail.
The results are shown in Figure 11.10. For delays exceeding 30 ms, there are initially spikes
TABLE 11.1
Peak Power Reduction with Added Power-Enable
PMOS Transistor
Peak
Power (mW)
Average
Power (mW)
Without power enable 109.1 5.1
With power enable 57.2 5.1
20.0
??’20.0
??’40.0
??’60.0
??’80.0
??’100
0
Current
with PE
Current
without PE
Current consumption with and without power enable
Branch (E??’ 6)
Times (E??’ 6)
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