0
??’50.0
??’75.0
??’100
??’125
??’150
??’175
0 25.0 50.0 75.0
Time (E??“6)
100 125 150
Branch (E??“6)
FIGURE 11.10
Supply current versus time for various delays of power-enable signals.
TABLE 11.2
Power Savings due to Architectural Improvements
Power consumption from naive implementation 1750 mW
Power consumption of banked memories 6.69 mW
Power consumption of address decoder 16.82 mW
Total optimized memory power consumption 23.51 mW
Power savings 98.7%
Minimum Energy=Power Considerations 207
the complexity of the protocol realization requiring additional area and cost in the ?¬?nal
implementation. Additionally, this complexity can impact the power consumption. Even
decisions about primitive opcode encoding can signi?¬?cantly impact power consumption
while only minimally impacting area.
With existing design ?¬‚ows, to gain an accurate estimate of power consumed for a
protocol implementation, the protocol must be designed, tested for correctness, implemented
in hardware, and ?¬?nally studied for power. This process can take months or years of
engineering effort to complete. RFID companies typically do not have this type of man
power to dedicate for this purpose.
In this section, we describe a power macromodeling technique that works in concert
with the RFID design automation ?¬‚ow described in Chapter 3.
As shown in that chapter, the RFID compiler, as illustrated in Figure 11.
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