11, allows the
RFID system designer to design and implement new RFID protocols in a matter of hours.
A team of design engineers without this tool would require months or longer. The team
would require additional time and effort to examine the power and area impacts of their
completed designs to optimize the tag.
However, the generation of the performance and area details of the design requires
specialized ASIC synthesis tools such as Synopsys Design Compiler, which must be
manually tuned to achieve good results. Performance and area may be estimated at this
level but require additional time and computer-aided design effort such as placement,
routing, and design rule checking with tools like Cadence SoC Encounter to get a more
accurate result. Achieving power consumption statistics requires an additional level of
effort by simulating the design and putting it through additional power estimation tools
such as Synopsys Nanosim, or HSPICE.
In the following subsections, a tool is described based on a power macromodeling
technique that calculates a power estimate at a much higher level during the design
automation process of the RFID compiler. The tool generates a behavioral representation
of the hardware that generates a custom simulator for the controller design generated by
the RFID compiler. Through access to a prepro?¬?led library of blocks in the target CMOS
process, the power consumption can be estimated 100 times faster than the fastest
ASIC power estimation ?¬‚ows.
Pages:
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407