FromFigure 11.13, it can be seen that the
most power is consumed by the adder when spatial correlation is low and transition density
is high. This shows that using transition density, d, alone for dynamic power optimization
can be insuf?¬?cient, although it is often considered the only metric of interest.
1.0
0.8
0.6
0.4
0.2
s
0.0
0.8
0.6
0.4
d
p
0.2
0.0
1.0
0.8
0.6
0.4
0.2
FIGURE 11.13
Four-dimensional plot of p, d, and s versus power for an adder synthesized as 0.16 mm OKI ASIC.
* The power pro?¬?les were originally published in Jones et al. [11].
210 RFID Handbook: Applications, Technology, Security, and Privacy
11.3.3 SystemC Simulator Construction
The SystemC simulator construction is completed in two phases. In the ?¬?rst phase, the
user-speci?¬?ed C behaviors that correspond to the different RFID primitives are converted
into SystemC designs. The compiler translates each super data ?¬‚ow graph (SDFG) into a
behavioral SystemC design.* This uses a SystemC abstract syntax tree (AST) for the
intermediate representation, which contains data structures that behave according to
the SystemC speci?¬?cation.
In the second phase, the compiler generates the simulator framework for the entire tag,
which includes the unpacking, decode, and packing logic. The compiler uses the information
in the input macros ?¬?le along with the SystemC AST data structures to generate this.
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