To
solve this problem we have developed an active tag architecture, as shown in Figure 11.15.
The goal is a tag system with essentially in?¬?nite battery shelf life and an active battery
life essentially equal to that of the tag. The overall architecture for such a tag is given in
Figure 11.15. This architecture is referred to as a passive active radio frequency identi?¬?cation
tag (PART). The system contains passive energy receiver called the burst switch
connected to the active transceiver. When RF energy is received on the passive receiver it
TABLE 11.3
Power Macromodeling versus Traditional Method
Primitives Collection Query
Power Macromodeling
Power (W) 3.42E06 1.68E04
Time (s) 0.12 0.41
Traditional Method
Power (W) 2.98E06 1.14E04
Time (s) 32.12 40.71
Times Speedup 267 99
212 RFID Handbook: Applications, Technology, Security, and Privacy
activates the active transceiver. This is described in more detail in Section 11.4.1. Once the
active transceiver is activated, the smart buffer keeps the main processing controller asleep
until it is needed for processing an incoming packet. The smart buffer is described in
Section 11.4.2. The controller may be a microprocessor, an ASIC, or even an FPGA,
depending on the particular application.
The operation of this architecture is as follows. When the tag is not interrogated the
battery power to the transceiver and smart buffer will be disconnected and the controller
will be in the sleep mode if processor or SRAM FPGA based or disconnected from power if
ASIC or Flash FPGA based.
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