For processor compatibility, it was desirable to
minimize the number of lines between the processor and the smart buffer. Thus, four (4)
parallel lines are used to communicate the processor to buffer command control.
The processor to smart buffer commands are illustrated in Figure 11.25. After waking up
the processor, the smart buffer listens for the processor to initiate commands for data
communication. As shown in Figure 11.25, the control unit decodes 4 bit processor
commands into ?¬?ve basic operations: transmit, update, push, pull, and null. The double
circle represents a potentially multicycle operation.
Based on different control commands, the unit determines the direction of the bidirectional
smart buffer, processor interface. In Figure 11.25, dir = 0 represents that the
direction of I/O is from processor to smart buffer and dir = 1 is the reverse. Because the
smart buffer and processor are operated in two different clock domains, a handshaking
communication approach is required to push/pull data to/from the FIFOs. Therefore, it is
TABLE 11.6
Packet Analysis Algorithm
for the ANSI Standard
Input Output
Opcode Process Command
30 If Group ID matcha
16 Yes
35 Yes
P2P If Tag ID match
a Group ID match always occurs if the
currently stored group ID within the
tag is zero.
222 RFID Handbook: Applications, Technology, Security, and Privacy
necessary to dedicate more than one cycle to transmit a single byte of data between the
processor and FIFO.
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